There is a great deal of work, the oldest dating back about 15 years, pertaining to hardware architectures for security. Many approaches exist, with various security objectives. Most of them rely on a hardware aid in the form of a cryptographic coprocessor or a complete virtual processor guaranteeing its isolation from the remainder of the world, as in the case of the TrustZone technology from the company ARM™.
Another solution belonging to the prior art is the XOM (execute-Only Memory) hardware architecture described in particular in the article by D. Lie, C. Thekkath, M. Mitchell, P. Lincoln, D. Boneh, J. Mitchell, and M. Horowitz entitled “Architectural Support for Copy and Tamper Resistant Software,” SIGPLAN Not., vol. 35, No. 11, pp. 168-177, November 2000. This technique offers guarantees of confidentiality by allowing blind execution of application package code, optionally including a complete virtual machine. The code and the data are stored in enciphered form in memory, and are enciphered/deciphered on the fly within the processor itself. Another existing solution is the AEGIS architecture described in the article by G. E. Suh, D. Clarke, B. Gassend, M. van Dijk, et S. Devadas entitled “AEGIS: Architecture for Tamper-evident and Tamper-resistant Processing,” in Proceedings of the 17th Annual International Conference on Supercomputing, New York, N.Y., USA, 2003, pp. 160-171. This architecture relies on the same principles but considers an even more severe threat model.
However, the need exists to find an alternative to these solutions so as to obtain higher performance with lower hardware cost.